Thermal Channel Noise of Quarter and Sub-Quarter Micron NMOS FET’s

We present a simple and efficient method for the extraction of thermal channel noise of MOS FET’s in quarter and sub-quarter micron technologies from NF50 (noise figure at 50 Ohm source resistance) measurements. For shorter channel lengths the experimental results shows a continuously rising deviation from the classical long channel theory [1]. For a 0.18 μm technology a γ≈6 instead of 2/3 in saturation was extracted (increase of factor 9 compared to the long channel theory). INTRODUCTION Due to continuous reduction of minimum channel length in CMOS technologies in the last years, CMOS has become a candidate for RF applications. For quarter and sub-quarter micron technologies transit frequencies (ft) in the range of 40-70 GHz and maximum oscillation frequencies up to 40 GHz and more are possible for NMOS transistors [2]. For these devices the classical assumption of thermal equilibrium in the calculation of the channel noise is questionable. Additional, so called hot carrier noise is observed for short channel transistors [3-6]. But until now only results for ≈0.8μm [3] or 0.5μm [4] technologies are available. In our paper for the first time results for quarter and sub-quarter micron technologies are presented. The reliability of this method is verified by comparing results from DC measurements (gd0 model) with results from RF noise measurements for almost ideal long channel transistors (1.05μm). In conclusion, the purpose of this work is to introduce an efficient extraction method for thermal channel noise of extreme short channel transistors and secondly to give necessary hints for RF–CMOS design, where finding the optimum between noise performance and AC performance is one of the key issues (e.g. LNA’s, which are an essential part of system on a chip solutions for wireless communication). MEASUREMENTS, TEST STRUCTURES AND DE-EMBEDDING A commercial noise figure measurement set up was used (ATN) and on wafer measurements from 600 MHz up to 6 GHz have been performed. This frequency range is high enough to clearly separate 1/f and white noise of our test structures (Tab.1). These test structures are optimized for RF applications (folded finger structures). The noise measurements are de-embedded with the noise deembedding method presented in [7]. Exact de-embedding of the noise measurements is very important, because the influence of the parasitics (pads and substrate resistors) on the NF50 value can be significant [8]. At the same structures also S-parameters are measured and deembedded with the usual standard method.